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ALPHA TEST ARCHITETTURA PDF

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A common classification is by architectural complexity. A complex instruction set computer CISC has many specialized instructions, some of which may only be rarely used in practical programs. A reduced instruction set computer RISC simplifies the processor by efficiently implementing only the instructions that are frequently used in programs, while the less common operations are implemented as subroutines, having their resulting additional processor execution time offset by infrequent use.

These architectures seek to exploit instruction-level parallelism with less hardware than RISC and CISC by making the compiler responsible for instruction issue and scheduling.

These are theoretically important types, but have not been commercialized. Instructions[ edit ] Machine language is built up from discrete statements or instructions.

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On the processing architecture, a given instruction may specify: particular registers for arithmetic, addressing, or control functions particular memory locations or offsets to them particular addressing modes used to interpret the operands More complex operations are built up by combining these simple instructions, which are executed sequentially, or as otherwise directed by control flow instructions.

Examples of operations common to many instruction sets include: Data handling and memory operations[ edit ] Set a register to a fixed constant value. Copy data from a memory location to a register, or vice versa a machine instruction is often called move; however, the term is misleading. Used to store the contents of a register, the result of a computation, or to retrieve stored data to perform a computation on it later.

Often called load and store operations. Read and write data from hardware devices. Add, subtract, multiply, or divide the values of two registers, placing the result in a register, possibly setting one or more condition codes in a status register. Perform bitwise operations , e. Compare two values in registers for example, to see if one is less, or if they are equal.

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Floating-point instructions for arithmetic on floating-point numbers. Branch to another location in the program and execute instructions there. Conditionally branch to another location if a certain condition holds.

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Indirectly branch to another location. Call another block of code, while saving the location of the next instruction as a point to return to. Perform coprocessor operations. Complex instructions[ edit ] Processors may include "complex" instructions in their instruction set.

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A single "complex" instruction does something that may take many instructions on other computers. Some examples of "complex" instructions include: transferring multiple registers to or from memory especially the stack at once complicated integer and floating-point arithmetic e. SIMD instructions, a single instruction performing an operation on many homogeneous values in parallel, possibly in dedicated SIMD registers performing an atomic test-and-set instruction or other read-modify-write atomic instruction instructions that perform ALU operations with an operand from memory rather than a register Complex instructions are more common in CISC instruction sets than in RISC instruction sets, but RISC instruction sets may include them as well.

RISC instruction sets generally do not include ALU operations with memory operands, or instructions to move large blocks of memory, but most RISC instruction sets include SIMD or vector instructions that perform the same arithmetic operation on multiple pieces of data at the same time. SIMD instructions have the ability of manipulating large vectors and matrices in minimal time.

SIMD instructions allow easy parallelization of algorithms commonly involved in sound, image, and video processing. Instruction encoding[ edit ] One instruction may have several fields, which identify the logical operation, and may also include source and destination addresses and constant values. This is the MIPS "Add Immediate" instruction, which allows selection of source and destination registers and inclusion of a small constant. On traditional architectures, an instruction includes an opcode that specifies the operation to perform, such as add contents of memory to register—and zero or more operand specifiers, which may specify registers , memory locations, or literal data.

The operand specifiers may have addressing modes determining their meaning or may be in fixed fields. In very long instruction word VLIW architectures, which include many microcode architectures, multiple simultaneous opcodes and operands are specified in a single instruction.

Instruction set architecture

Some exotic instruction sets do not have an opcode field, such as transport triggered architectures TTA , only operand s. The Forth virtual machine and other " 0-operand " instruction sets lack any operand specifier fields, such as some stack machines including NOSC.

For example, a conditional branch instruction will be executed, and the branch taken, if the condition is true, so that execution proceeds to a different part of the program, and not executed, and the branch not taken, if the condition is false, so that execution continues sequentially.

Some instruction sets also have conditional moves, so that the move will be executed, and the data stored in the target location, if the condition is true, and not executed, and the target location not modified, if the condition is false.

A few instruction sets include a predicate field in every instruction; this is called branch predication. Number of operands[ edit ] Instruction sets may be categorized by the maximum number of operands explicitly specified in instructions. In the examples that follow, a, b, and c are direct or calculated addresses referring to memory cells, while reg1 and so on refer to machine registers.

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For stack machines, the terms "0-operand" and "zero-address" apply to arithmetic instructions, but not to all instructions, as 1-operand push and pop instructions are used to access memory.

This effectively 'stores' the result without an explicit store instruction. RISC — Requiring explicit memory loads, the instructions would be: load a,reg1; load b,reg2; add reg1,reg2; store reg2,c.

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Unlike 2-operand or 1-operand, this leaves all three values a, b, and c in registers available for further reuse. Each instruction specifies some number of operands registers, memory locations, or immediate values explicitly. Some instructions give one or both operands implicitly, such as by being stored on top of the stack or in an implicit register.

If some of the operands are given implicitly, fewer operands need be specified in the instruction. When a "destination operand" explicitly specifies the destination, an additional operand must be supplied.

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Consequently, the number of operands encoded in an instruction may differ from the mathematically necessary number of arguments for a logical or arithmetic operation the arity. Operands are either encoded in the "opcode" representation of the instruction, or else are given as values or addresses following the instruction.

Register pressure[ edit ] Register pressure measures the availability of free registers at any point in time during the program execution. Register pressure is high when a large number of the available registers are in use; thus, the higher the register pressure, the more often the register contents must be spilled into memory.

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